| Course Code |
CSC332 |
| Course Title |
Digital Logic Design |
| Credit Hours |
3+1 |
| Prerequisites by Course(s) and Topics |
Applied Physics |
| Assessment Instruments with Weights (homework, quizzes, midterms, final, programming assignments, lab work, etc.) |
SESSIONAL (Quizzes, Assignments, Presentations) =25 %
Midterm Exam =25 %
Final Exam = 50%
|
| Course Coordinator |
Maria Tariq |
| URL (if any) |
|
| Current Catalog Description |
Digital fundamentals Floyd (11th edition) |
| Textbook (or Laboratory Manual for Laboratory Courses) |
Digital fundamentals Floyd (11th edition) |
| Reference Material |
1. Digital Fundamentals by Floyd, 11/e. 2. Fundamental of Digital Logic with Verilog Design, Stephen Brown, 2/e. |
| Course Goals |
The Goals of the course is: to teach students the fundamental concepts in classical digital design and to demonstrate clearly the way in which digital circuits are designed and analyzed today. The purpose is to make students familiar with modern hierarchy of digital hardware and enlighten them the state-of-the-art computer hardware design methodologies. Moreover, the contents of the course provide students the basic idea of how to design and simulate logic circuits. |
| Course Learning Outcomes (CLOs): |
| At the end of the course the students will be able to: | Domain | BT Level* |
|---|
| Explain fundamental concepts of digital logic design. |
C |
2 |
| Demonstrate the acquired knowledge to apply techniques related to the design and analysis of digital electronic circuits . |
C |
3 |
| Analyze small-scale combinational and sequential digital circuits. |
C |
4 |
| * BT= Bloom’s Taxonomy, C=Cognitive domain, P=Psychomotor domain, A= Affective domain |
|
|
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| Topics Covered in the Course, with Number of Lectures on Each Topic (assume 15-week instruction and one-hour lectures) |
| Week | Lecture | Topics Covered |
|---|
| Week 1 |
1 |
Introduction, Binary Numbers, |
|
2 |
Number Conversion, Decimal Numbers |
| Week 2 |
3 |
1’s and 2’s Complements, Arithmetic Operations with unsigned numbers |
|
4 |
Arithmetic Operations with signed numbers |
| Week 3 |
5 |
Octal & Hexadecimal number |
|
6 |
Conversions, Binary Coded Decimal (BCD) |
| Week 4 |
7 |
The Inverter, AND, OR gates |
|
8 |
NOR and NAND XOR and XNOR gates |
| Week 5 |
9 |
Boolean Algebra Rules, DeMorgan’s Theorem |
|
10 |
Simplification using Boolean algebra |
| Week 6 |
11 |
Karnaugh Map, SOP and POS expressions, standardization of logic expressions |
|
12 |
Karnaugh Map, SOP, POS minimization 3 variable k-maps and 4 variable k-maps |
| Week 7 |
13 |
5-varible k-maps and simplification of logic circuits using k-maps |
|
14 |
Basic Combinational logic circuits Designing of Combinational logic circuits |
| Week 8 |
1 hours |
Mid Term |
| Week 9 |
15 |
Universal property of NAND gates and NOR gates |
|
16 |
Combinational logic using NOR gates, Combinational logic using NOR gates |
| Week 10 |
17 |
Basic Adders, Half Adders Full Adders |
|
18 |
Parallel Binary Adders, Basic Subtractions |
| Week 11 |
19 |
Mid term |
|
20 |
Mid term |
| Week 12 |
21 |
Logic Comparators and Logic Multipliers |
|
22 |
Decoders |
| Week 13 |
23 |
Encoder |
|
24 |
Multiplexer or Data selector |
| Week 14 |
25 |
De-Multiplexer, Application of MUX and DeMUX |
|
26 |
Latches |
| Week 15 |
27 |
Gated Latches, Edge-Triggered Flip Flops |
|
28 |
Edge-Triggered Flip Flops D-Flip flop |
| Week 16 |
29 |
S-R Flip Flops, J- K Flip Flops |
|
30 |
SISO shift registers, SIPO shift registers PIPO shift registers. |
| Week 17 |
2 hours |
Final Term |
|
| Laboratory Projects/Experiments Done in the Course |
|
| Programming Assignments Done in the Course |
|
