| Course Code |
CSC332 |
| Course Title |
Digital Logic Design |
| Credit Hours |
3+1 |
| Prerequisites by Course(s) and Topics |
Applied Physics |
| Assessment Instruments with Weights (homework, quizzes, midterms, final, programming assignments, lab work, etc.) |
SESSIONAL (Quizzes, Assignments, Presentations) =25 %
Midterm Exam =25 %
Final Exam = 50%
|
| Course Coordinator |
Muhammad Waheed ul Hassan |
| URL (if any) |
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| Current Catalog Description |
|
| Textbook (or Laboratory Manual for Laboratory Courses) |
Laboratory Manual |
| Reference Material |
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| Course Goals |
The aim of lab sections is to familiarize with tools and technologies to verify and implement the concepts covered in theory section. This course is to provide background in Digital Logic Design to improve students’ learning outcomes and critical thinking by understanding and analysis of digital logic fundamentals, Combinational logic, and sequential circuits. |
| Course Learning Outcomes (CLOs): |
| At the end of the course the students will be able to: | Domain | BT Level* |
|---|
| Demonstrate proficiency in constructing and testing digital logic circuits using logic gates, other hardware components and simulation software, following proper safety and procedural guidelines. |
P |
1 |
| Apply problem-solving skills to Design and Implement Combinational Logic effectively |
P |
2 |
| Design and implement sequential logic circuits using appropriate hardware components, tools, and techniques, and analyze their behavior in response to different input stimuli for proper functionality. |
P |
2 |
| * BT= Bloom’s Taxonomy, C=Cognitive domain, P=Psychomotor domain, A= Affective domain |
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| Topics Covered in the Course, with Number of Lectures on Each Topic (assume 15-week instruction and one-hour lectures) |
| Week | Lecture | Topics Covered |
|---|
| Week 1 |
1 |
AND Gate Operation |
|
2 |
OR Gate Operation |
| Week 2 |
3 |
NOT Gate Operation |
|
4 |
NAND Gate Operation |
| Week 3 |
5 |
NOR Gate Operation |
|
6 |
XOR Gate Operation |
| Week 4 |
7 |
Construction of XOR Gate from NAND Gate |
|
8 |
Complements, Arithmetic Operations with unsigned numbers |
| Week 5 |
9 |
K-Map with 2 Variables |
|
10 |
K-Map with 3 Variables |
| Week 6 |
11 |
K-Map with 4 Variables |
|
12 |
K-Map with 5 Variables |
| Week 7 |
13 |
Half Adder Operation |
|
14 |
Full Adder Operation |
| Week 8 |
1 hours |
Mid Term |
| Week 9 |
15 |
Half Subtractor Operation |
|
16 |
Full Subtractor Operation |
| Week 10 |
17 |
7-Segment Display Operation |
|
18 |
Decoder Operation |
| Week 11 |
19 |
BCD to 7-Segment Display |
|
20 |
Multiplexer Gate Operation |
| Week 12 |
21 |
Using Multiplexer and Demultiplexer/Decoder |
|
22 |
Multiplexing 7-Segment Displays |
| Week 13 |
23 |
Comparator Operation |
|
24 |
D Latch and Flip Flop Operation |
| Week 14 |
25 |
Latching BCD Data for displaying 7-Segment Display |
|
26 |
Recalculating Data |
| Week 15 |
27 |
J-K Flip Flop Operation |
|
28 |
Random Access Memories |
| Week 16 |
29 |
Frequency Counter Design |
|
30 |
T Flip Flop Operation |
| Week 17 |
2 hours |
Final Term |
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| Laboratory Projects/Experiments Done in the Course |
Yes |
| Programming Assignments Done in the Course |
N/A |
