Week 1 |
1 |
Introduction, Binary Numbers, |
|
2 |
Number Conversion, Decimal Numbers |
Week 2 |
3 |
1’s and 2’s Complements, Arithmetic Operations with unsigned numbers |
|
4 |
Arithmetic Operations with signed numbers |
Week 3 |
5 |
Octal & Hexadecimal number |
|
6 |
Conversions, Binary Coded Decimal (BCD) |
Week 4 |
7 |
The Inverter, AND, OR gates |
|
8 |
NOR and NAND XOR and XNOR gates |
Week 5 |
9 |
Boolean Algebra Rules, DeMorgan’s Theorem |
|
10 |
Simplification using Boolean algebra |
Week 6 |
11 |
Karnaugh Map, SOP and POS expressions, standardization of logic expressions |
|
12 |
Karnaugh Map, SOP, POS minimization 3 variable k-maps and 4 variable k-maps |
Week 7 |
13 |
5-varible k-maps and simplification of logic circuits using k-maps |
|
14 |
Basic Combinational logic circuits Designing of Combinational logic circuits |
Week 8 |
1 hours |
Mid Term |
Week 9 |
15 |
Universal property of NAND gates and NOR gates |
|
16 |
Combinational logic using NOR gates, Combinational logic using NOR gates |
Week 10 |
17 |
Basic Adders, Half Adders Full Adders |
|
18 |
Parallel Binary Adders, Basic Subtractors |
Week 11 |
19 |
Logic Comparators and Logic Multipliers |
|
20 |
Decoders |
Week 12 |
21 |
Encoder |
|
22 |
Multiplexer or Data selector |
Week 13 |
23 |
De-Multiplexer, Application of MUX and DeMUX |
|
24 |
Latches |
Week 14 |
25 |
Gated Latches, Edge-Triggered Flip Flops |
|
26 |
Edge-Triggered Flip Flops D-Flip flop |
Week 15 |
27 |
S-R Flip Flops, J- K Flip Flops |
|
28 |
SISO shift registers, SIPO shift registers PIPO shift registers. |
Week 16 |
29 |
Synchronous/Asynchronous counter operation |
|
30 |
Real-time logic and arithmetic circuits implementation, Programmable Logic Devices |
Week 17 |
2 hours |
Final Term |