| Course Code |
CSC332 |
| Course Title |
Digital Logic Design |
| Credit Hours |
3+1 |
| Prerequisites by Course(s) and Topics |
Basic Electronics/Applied Physics |
| Assessment Instruments with Weights (homework, quizzes, midterms, final, programming assignments, lab work, etc.) |
SESSIONAL (Quizzes, Assignments, Presentations) =25 %
Midterm Exam =25 %
Final Exam = 50%
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| Course Coordinator |
Hassan Sultan |
| URL (if any) |
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| Current Catalog Description |
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| Textbook (or Laboratory Manual for Laboratory Courses) |
1. Text Book Logic and Computer Design Fundamentals by M. Mano 2nd edition Publisher Prentice Hall 2. Other Resources/Reference Books Digital fundamentals Floyd (9th edition) |
| Reference Material |
3. Other Resources/Reference Books Digital fundamentals Floyd (9th edition) |
| Course Goals |
1. Intrduce the concept of digital and binary systems 2. Be able to design and analyses combinational logic circuits. 3. Be able to design and analyses sequential logic circuits. 4. Understand the basic software tools for the design and implementation of digital circuits and systems. 5. Reinforce theory and techniques taught in the classroom through experiments and projects in the laboratory. |
| Course Learning Outcomes (CLOs): |
| At the end of the course the students will be able to: | Domain | BT Level* |
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| 1. Students can analyse digital logic circuits. |
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| 2. Students can design digital logic circuits. |
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| 3. Students can write and interpret documentation for digital systems. |
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| 4. Students can implement and test digital circuits |
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| 5. Students will be able to understand the design principles and techniques used for Arithmetic and logic unit of computer |
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| * BT= Bloom’s Taxonomy, C=Cognitive domain, P=Psychomotor domain, A= Affective domain |
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| Topics Covered in the Course, with Number of Lectures on Each Topic (assume 15-week instruction and one-hour lectures) |
| Week | Lecture | Topics Covered |
|---|
| Week 1 |
1 |
AND Gate Operation |
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2 |
OR Gate Operation |
| Week 2 |
3 |
NOT Gate Operation |
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4 |
NAND Gate Operation |
| Week 3 |
5 |
NOR Gate Operation |
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6 |
XOR Gate Operation |
| Week 4 |
7 |
Construction of XOR Gate from NAND Gate |
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8 |
Half Adder Operation |
| Week 5 |
9 |
Full Adder Operation |
|
10 |
Full Adder Operation |
| Week 6 |
11 |
Decoder Operation |
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12 |
Decoder Operation |
| Week 7 |
13 |
BCD to 7-Segment Display |
|
14 |
BCD to 7-Segment Display |
| Week 8 |
1 hours |
Mid Term |
| Week 9 |
15 |
Combinational logic using NOR gates |
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16 |
Combinational logic using NOR gates |
| Week 10 |
17 |
Multiplexer Operation |
|
18 |
Multiplexer Operation |
| Week 11 |
19 |
Multiplexer Operation Using Multiplexer and Demultiplexer/Decoder. |
|
20 |
Multiplexer Operation Using Multiplexer and Demultiplexer/Decoder. |
| Week 12 |
21 |
J-K Flip Flop Operation |
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22 |
J-K Flip Flop Operation |
| Week 13 |
23 |
. D Latch |
|
24 |
. D Latch |
| Week 14 |
25 |
Flip Flop Operation |
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26 |
Flip Flop Operation |
| Week 15 |
27 |
Random Access Memories Frequency Counter Design |
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28 |
Random Access Memories Frequency Counter Design |
| Week 16 |
29 |
Latching BCD Data for Displaying 7-segment |
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30 |
Revision |
| Week 17 |
2 hours |
Final Term |
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| Laboratory Projects/Experiments Done in the Course |
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| Programming Assignments Done in the Course |
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